Western Digital has announced that it’s completed work on its Swerv RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design. Publishing the RTL code allows other companies to use the design.
Open-source hardware initiatives and ISAs have existed for decades, but RISC-V has gathered a critical ecosystem and corporate interests in these projects where historically there was little incentive to buy-in. The issue isn’t primarily cost savings — particularly as node sizes decrease, the licensing costs of an ARM core simply aren’t a major part of the total. The end of conventional Moore’s Law scaling has moved interest back to ISAs, as has the rise of IoT, AI, ML, and the need for new architectures to address these challenges.
Western Digital has published a whitepaper to share some of its own thoughts on this topic. It focuses on the modularity, customizable, configurable nature of the RISC-V ISA before stating:
As Big Data and Fast Data applications start to create more extreme workloads, purposebuilt architectures will be required to pick up where today’s general-purpose architectures have reached their limit. Applications which require analytics, machine learning, artificial intelligence and smart systems demand purpose-built architectures.
Building out a full ecosystem for an ISA takes time, however, which is why the first commercial RISC-V cores we’re seeing in-market focus on smaller niches. In this case, Swerv is intended to support real-time surveillance operations, power IoT devices, and perform real-time analytics on edge data.
Western Digital’s Swerv is a low-power, in-order design with a two-way superscalar architecture and an eight-stage pipeline. If implemented in 28nm technology, it can clock up to 1.8GHz. Simulated performance is said to 4.9 CoreMark/MHz, which would make this CPU a bit faster than ARM’s older Cortex-A15.
Western Digital is also announcing its own OmniXtend cache coherent memory technology, which allows cache coherency to be maintained over Ethernet networks. This capability was co-developed with another major player in the RISC-V ecosystem, SiFive, and should be extendable to address other types of accelerators as well.
Since hardware isn’t very useful without software to run on it, Western Digital is opening up the Swerv Instruction Set Simulator. It’s a software program for simulating code execution on Swerv cores, accelerating overall time to development. While we you shouldn’t expect to see these cores popping up in mainstream PCs, WD’s Swerv could have an interesting role to play in storage devices of the future — as could RISC-V. Western Digital’s Github project can be found here.
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