IBM researchers announced a new manufacturing breakthrough yesterday that could clear the way to 5nm device scaling and the implementation of next-generation transistor design technologies. The company has used silicon nanosheets — sheets of 2D silicon stacked on top of one another — to assemble a test chip with 30 billion transistors, compared with a 7nm, 20-billion transistor chip the research team debuted several years ago.
According to the research team, the use of nanosheets allows them to create gate-all-around (GAA) FETs, which are broadly believed to be the most likely follow-up to the FinFET technology cutting-edge silicon designs use today. The diagram below shows the progression from a traditional 2D transistor (left) to a FinFET structure (right), to a GAAFET (bottom).
The structure of the IBM nanosheet design means that the fin, which formerly stuck “up” out of the transistor, is now effectively a silicon nanowire. The test chip was also built using EUV — an important step for the technology, given the difficulties we’ve seen with ramping EUV production overall. IBM claims that using EUV allows the company to adjust the width of the silicon nanosheets continuously, and that its new GAA approach and EUV allow for flexibility that current semiconductor designs can’t match. The company expects EUV + GAA to provide superior scaling compared with FinFETs at the same process node. That’s something other companies seem to agree with, given that Samsung is planning its own transition to GAA FETs at the 5nm node.
“This announcement is the latest example of the world-class research that continues to emerge from our groundbreaking public-private partnership in New York,” said Gary Patton, CTO and head of worldwide RD at GlobalFoundries. “As we make progress toward commercializing 7nm in 2018 at our Fab 8 manufacturing facility, we are actively pursuing next-generation technologies at 5nm and beyond to maintain technology leadership and enable our customers to produce a smaller, faster, and more cost efficient generation of semiconductors.”
IBM also claims that compared with existing 10nm technology, its 5nm tech can offer 40 percent improved performance at the same power consumption or 75 percent power savings at the same performance level as current designs. This inadvertently highlights the ongoing difficulty of improving raw performance in silicon today. When the performance headroom enabled by a new type of transistor design and the use of cutting-edge lithography equipment is nearly half of the potential power savings, it’s clear the industry has a scaling problem that won’t be easily ameliorated, even as node sizes continue to shrink.
As for when we’ll see these breakthroughs in shipping products, the gap between announcement and ship date remains significant. Consider, for example, that IBM made critical 7nm announcements nearly two years ago, yet we’re only recently seeing 10nm hardware in-market. The rollout of 5nm still seems to be targeting 2020 or 2021. And if that rollout depends on EUV being ready, it could be further delayed. Given that ultraviolet lithography is literally more than a decade late, it’s simply not clear all the problems have finally been fixed and the road cleared to full manufacturing integration. It’s more likely that EUV will roll out in stages and be used for critical steps first before full mainstream integration.
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