Chiplets are the Future, But They Won’t Replace Moore’s Law

AMD Epyc

At AMD’s New Horizons event this week, the company made a major announcement about the organization and structure of its upcoming Epyc CPUs. Going forward, Epyc will use a single die for I/O and logic, with its CPU cores and caches organized into “chiplets.” While AMD has not revealed every last detail of chiplet organization, we’ve shown some shots of the concept.

One interesting tidbit with this core arrangement is that AMD is also obviously keeping the number of cores per chiplet the same — the Epyc 2 the company has demonstrated packs eight chiplets around a central I/O platform, working out to eight die per core. There’s an obvious trade-off to this method. First, AMD will have equal latency to all 64 cores, without any of the variation we saw on previous Epyc parts, where the number of “hops” between the DDR4 memory controller and the CPU core requesting the data changes how long it takes for data to be delivered. But the flip side to this is that latency will be nominally higher across the chip. AMD could theoretically mitigate some of this penalty with changes to Infinity Fabric, but while the company confirmed that it made some adjustments and changes to how IF operates with second-gen Epyc, it didn’t give details on them.

AMD’s shift to chiplets has been hailed as a breakthrough by some, but I don’t think that characterization is entirely accurate. In fact, I’d argue that their adoption is actually a partial reversal of an earlier trend. Beginning in the late 1990s, Intel and AMD brought certain features, like L2 cache, on-die to improve their performance. This continued with integrated memory controllers, GPU functionality, and other aspects of the northbridge and southbridge that used to live in their own silicon. Multi-Chip Modules — say, a quad-core chip actually comprised of two dual-cores connected together — have existed for over a decade. True, AMD is doing something somewhat different here by breaking out I/O functionality, but that doesn’t change the fact that we’re taking a step backwards to a previous, less-integrated method of building microprocessors. The fact that we’re doing it for very good reasons doesn’t change the implications for semiconductor manufacturing as a whole.

There are positive reasons for why AMD adopted chiplets — they improve yield and cost compared to enormous monolithic dies and they’re inherently cheaper to manufacture since they waste less wafer space (smaller chips result in less wasted wafer as a percentage of the total). But there’s also a negative reason that speaks to the difficulty of current scaling: We’ve reached the point where it simply makes little sense to continue scaling down wire sizes. Every time we perform a node shrink, the number of designs that benefit from the shift are smaller. AMD’s argument with Rome is that it can get better performance scaling and reduce performance variability by moving all of its I/O to this single block, and that may well be true — but it’s also an acknowledgment that the old trend of assuming that process node shrinks were just unilaterally good for the industry is well and truly at an end.

Is there a positive story around chiplets? Absolutely. But there’s no arguing that the positive story exists in the context of an overarching situation in which chip manufacturers are required to twist themselves into knots to find ways to move the ball forward half as much as they used to, while spending 5-10x the cash and three times the effort. Chiplets are the future and AMD could even hypothetically deploy heterogeneous chiplet solutions, with some CPU cores on the same package replaced by GPU cores, AI accelerators, or other types of silicon. But we’re in this position in the first place because the old scaling rules no longer apply, and no one has figured out a solution to that problem yet. Moore’s law may have carried us along the last decade, but it was Dennard Scaling that made semiconductors faster and less power-hungry, year after year. With density improvements unknown past 5nm and Dennard Scaling having died in 2005, the road ahead only gets harder from here — and that’s not a problem chiplets from any vendor are going to be able to solve.

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